1. Field of Invention
The present invention relates to a data latch circuit for sampling and holding a signal at a desired timing. In particular, the present invention relates to, in an active matrix display device for displaying an image with the use of a digital image signal, a data latch circuit for sampling and holding the digital image signal. Moreover, the present invention relates to an electronic appliance using an active matrix display device having a driver circuit including the data latch circuit.
2. Description of the Related Art
In recent years, techniques for forming a thin film transistor (TFT) over an insulating substrate have drastically progressed, and development of a flat panel display typified by a liquid crystal display device or the like has been promoted in view of the increase in demand of flat panel displays for mobile appliances. In particular, development of techniques for integrally forming a pixel portion for displaying an image and a driver circuit for controlling the pixel portion (hereinafter the pixel portion and the driver circuit are collectively referred to as an internal circuit) over one substrate has been actively promoted.
The internal circuit is connected to a controller IC or the like provided externally (hereinafter referred to as an external circuit) through a flexible printed circuit (FPC) or the like, and the internal circuit is controlled by the external circuit. In recent years, with size reduction of a semiconductor device, the size of an integrated circuit is getting smaller, which results in the advance in application thereof to mobile terminals and the like. Accordingly, further reduction in power consumption is required. Currently, drive voltage of an IC used in the external circuit generally is lower than drive voltage of the internal circuit.
In general, the external circuit outputs a signal with an amplitude of about 3.3 V while the internal circuit needs a drive voltage of about 5 to 10 V, which is higher than the amplitude of the signal outputted from the external circuit. Moreover, the internal circuit needs a data latch circuit for sampling a data signal in a low-amplitude digital form at a desired timing and holding the data signal for a certain period.
Some of data latch circuits are made in consideration of low amplitude signal input (see, for example, Patent Document 1: Japanese Patent Application Laid-Open No. 2000-352957).
However, a data latch circuit corresponding to low signal voltage input causes an error by variation in TFT characteristics, particularly variation in the threshold. Moreover, although the data latch circuit responds to such an error by increasing the amplitude of a signal with the use of a level conversion circuit or the like in accordance with drive voltage of an internal circuit, additional use of such a level conversion circuit or the like increases the expansion of a circuit scale and the increase in power consumption. Therefore, it is desirable to perform normal operation by inputting a low-amplitude signal from an external circuit to an internal circuit without any change.
Here, a conventional general data latch circuit is shown in FIGS. 2A and 2B. An equivalent circuit of a circuit symbol used in FIG. 2A is shown in FIGS. 15A, 15B, and 15C. In FIGS. 15A, 15B, and 15C, as drive power source, a positive power source is denoted by VDD while a negative power source is denoted by VSS.
Operation of the data latch circuit shown in FIG. 2A is briefly described using a timing chart shown in FIG. 2B. In a T1 period shown in FIG. 2B, a sampling (SAMP) signal is set at a high (H) level and an inverted sampling (SAMPB) signal is set at a low (L) level. A clocked inverter 200 operates as an inverter and inverts a data (DATA) signal and outputs the inverted data signal. In the case of using an analog switch 200a, the data (DATA) signal is outputted without any change. At this time, an output waveform in the case of using the clocked inverter 200 is shown by “a” in FIG. 2B as a state of a “node a” in FIG. 2A. Subsequently, an inverter 201 further inverts a state of the “node a” and outputs it to an output terminal (OUT). At this time, an output waveform in the case of using the clocked inverter 200 is denoted by OUT of FIG. 2B as a state of the OUT of FIG. 2A. Output waveforms of the “node a” and the OUT in the case of using the analog switch 200a are omitted because the waveforms are the inversion of the waveforms of the “node a” and the OUT shown in FIG. 2B. At this time, since the output of the clocked inverter 202 has high impedance, the output of the clocked inverter 200 or the analog switch 200a is not interrupted.
Subsequently, a T2 period starts, and when the sampling (SAMP) signal is at the low (L) level and the inverted sampling (SAMPB) signal is at a high (H) level, the output of the clocked inverter 200 or the analog switch 200a has high impedance; therefore, sampling the data (DATA) signal stops. At this time, an output in which the data (DATA) signal just before the termination of the T1 period has been inverted by the clocked inverter 200 appears, and the signal is further inverted by the inverter 201 and then outputted. On the other hand, the clocked inverter 202 operates as an inverter to form a loop with the inverter 201. An input of the inverter 201, i.e., a state of the “node a” is determined by the clocked inverter 202 while an input of the clocked inverter 202, i.e., a state of an output terminal (OUT) is determined by the inverter 201. This state continues during the T2 period and the DATA signal just before the termination of the T1 period is held.
After that, when the sampling (SAMP) signal is set at the high (H) level and the inverted sampling (SAMPB) signal is set at the low (L) level again in a T3 period, the clocked inverter 200 or the analog switch 200a operates similarly to the T1 period to sample the data (DATA) signal at that time and output the sampled data signal to the “node a” in an inverted state or not. When a T4 period starts, a DATA signal just before the termination of the T3 period is held by similar operation.
The above operation is repeated depending on the states of the sampling (SAMP) signal and the inverted sampling (SAMPB) signal, whereby sampling and holding the data (DATA) signal are repeated.
However, the amplitude of a video signal or the like is lower than the power source voltage of a logic element. If a video signal with small amplitude is held in a data latch circuit without any change, through current flows to a logic element in a data holding portion, thereby increasing the power consumption.